We develop cell and library design methodology that features low-power and ESD, and design and support libraries for LSI chips.
We also provide support for other companies' foundries, and support customized specifications.
|Low-Power Methodology||Development of Power Gating and Voltage Control Systems
Cell and Library Design Kits for Low-power applications
|ESD Methodology||Development of ESD Checker for Chip Verification
Development of Protective Elements with New Structures
|Cell Design Technology||Development of Small-area, Low Power Cell Libraries
Introduction of Non-Sony Library IP
|Library Methodology||Development of Accurate Library Modeling
Development of Low Power, New-structure Libraries