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Analog Technology


Outcome of Our Analog IP Design

Advanced LSIs embedded with our Analog IPs are used for various Sony products.

Feature of Analog IP

ADC
- Very Low Power 30mW (12bit 50MS/s)
34mW (8bit 300MS/s)
- Very Low Voltage Operation 0.7V Operation
- High-accuracy Operation 16bit Delta Sigma for Sensors
PLL
We optimize PLL design for various applications.
We can estimate the jitter value using our simulation technology.
- High Speed 2.4GHz
- Low jitter (TIE) Less than 10ps.rms

Our ADC Paper Presented at ISSCC2006/2008

A 30mW 12b 40MS/s Subranging ADC with a High-Gain Offset-Canceling Postive-Feedback Amplifier in 90nm Digital CMOS ISSCC2006.

A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS ISSCC2008.



PLL Design Technology

We optimized PLL design for various applications using our low jitter and low power technologies.

ADC List

Application Resolution FS[MS/s] Process
HDD/BD 6bit 600 90n
HDD/BD 6bit 1000 90n
Communication 8bit 300 65n
Communication/Video 10bit 300 65n
Controller 10bit 1 90n
Controller 10bit 1 65n
Controller 10bit 1 40n
Communication 12bit 40 90n
DSC 14bit 50 180n
Audio 16bit 0.096 130n

DAC List

Application Resolution FS[MS/s] Process
Video 12bit 50 90n
Video 12bit 50 65n
Video 10bit 54 40n

PLL List

Input Frequency
[MHz]
Output Frequency
[MHz]
TIE Jitter[ps-rms] Notes
4 400 10 Low Comparison
Frequency Low Jitter
10 800 10 Low Comparison
Frequency Low Jitter
6 950 - System Clock
30 720 - System Clock
74.25 2376 5 Higy Frequency
Low Jitter
148.5 2376 5 High Frequency
Low Jitter